1. Field of the Invention
The current invention generally relates to Read Only Memory (ROM). In particular, the current invention relates to improving performance of a ROM by reducing loading variation on bit lines.
2. Description of the Related Art
Modern electronic systems, such as digital computers frequently have a need for Read Only Memory (ROM), sometimes also known as Read Only Storage (ROS). A ROM is a semiconductor array that is personalized during manufacture of a semiconductor chip containing the ROM, and cannot be subsequently changed (i.e. written to a different value).
A ROM produces a fixed output for a particular input. For example, an exemplary ROM receives an ASCII (American Standard Code for Information Interchange) character and outputs a number of bits that are coupled to a display, such as an LCD (Liquid Crystal Display), an LED (Light Emitting Diode) display, or a CRT (Cathode Ray Tube). The display is controlled by the bits driven by the ROM in such a way as to present a picture of the particular ASCII character for a user of the electronic system having the display. In another application, a computer instruction, or a portion of the computer instruction, is input to a ROM. Responsive to the computer instruction input to the ROM, the ROM outputs bits that control logic circuits in the electronic system to execute the computer instruction.
A ROM comprises an address input that is decoded such that a particular word line of a plurality of word lines is activated. Each word line in the plurality of word lines controls a switching element, typically a Field Effect Transistor (FET). Each switching element, if appropriately coupled to a bit line, is capable of discharging the bit line from a precharged state. If a particular switching element is not coupled to its particular bit line, the particular switching element can not discharge the bit line from the precharged state.
FIG. 1A shows a portion of a prior art ROM 10. Bit lines BLx0 and BLx1 are precharged by PFETs (P-channel Field Effect Transistors) Pxa and Pxb under control of a precharge signal PCx. While PCx is active (“0” in the example shown), Pxa and Pxb conduct, precharging bit lines BLx0 and BLx1. All word lines WLx0–WLx3 must be inactive (“0” in the example shown) while precharge signal PCx is active. A word line that is active when, precharge signal PCx is active would cause a bit line having a switch (an NFET (N-channel Field Effect Transistor) in the example of FIG. 1) controlled to discharge that bit line when that word line is active to contend with the current of precharge of the PFET that is trying to charge the bit line.
For example, if WLx0, in the group of word lines WLx0–WLx3 that are driven by an address decode (not shown), is active when precharge signal PCx is active, Nxa0 and Nxb0 will cause some or all of the currents of Pxa and Pxb to flow to ground, rather than having the currents of Pxa and Pxb precharge bit lines BLx0 and BLx1 as desired.
In the exemplary prior art ROM of FIG. 1A, during an evaluate phase when PCx is inactive (“1”), one of the word lines WLx0–WLx3 will be activated, and bit lines BLx0 and BLx1 will output a pattern dependent on how the switches controlled by the active word line are personalized. The personalization is done during manufacturing of the ROM.
In the exemplary ROM 10, NFETs Nxa0 and Nxb0 have gates coupled to word line WLx0; sources coupled to ground; and drains coupled to BLx0 and BLx1 respectively. Each drain (or, as explained later, a source) coupled to a bit line adds a load. Since both Nxa0 and Nxb0 will be made conductive by an active word line WLx0, and, since Pxa and Pxb are nonconducting (PCx is inactive when word line WLx0 is active), BLx0 and BLx1 are discharged to ground through Nxa0 and Nxb0, respectively.
Similarly, when WLx1 is activated during the evaluate phase, bit line BLx1 will be discharged through NFET Nxb1. Bit line BLx0 will not be discharged, since NFET Nxa1 is not coupled to bit line Nxb0. In a similar manner, bit line BLx1 will be discharged when WLx2 or WLx3 is activated during the evaluate phase by Nxb2 or Nxb3, respectively. Bit line BLx0 will not be discharged when WLx2 or WLx3 is activated during the evaluate phase because Nxa2 and Nxa3 are not coupled to bit line BLx0.
Bit line BLx0 is loaded only by capacitances of a drain of Pxa, a drain of Nxa1, and miscellaneous other parasitic capacitances between BLx0 and other wiring near bit line BLx0. Bit line BLx1 is loaded by capacitances of a drain of Pxb, and drains of Nxb0, Nxb1, Nxb2, and Nxb3, as well as other parasitic capacitances between bit line BLx1 and other wiring near bit line BLx1. Although only four word lines are shown for simplicity, typical bit lines may be programmed to be discharged or not discharged by a relatively large number of word lines, for examples, 16, 32, 64, or 128 word lines. Therefore there can be a very wide range in capacitive loading from one bit line to another bit line.
As shown in FIG. 1B, timings, even on a simple ROM, depend heavily on bit line capacitive loading. Using signals on nodes from FIG. 1A to illustrate timings, PCx drops at a first time, and must stay active long enough (PCx Min in FIG. 1B) to charge the most heavily loaded bit line; BLx1 in the example. BLx0 is precharged long before PCx is eventually allowed to go inactive. Word lines, as explained earlier, must not be allowed to go active until the precharge (PCx) goes inactive. When PCx is inactive, a word line, e.g., WLx0 goes active. Responsive to WLx0 going active, bit lines BLx0 and BLx1 are discharged. It will be noted that BLx1, being much more heavily loaded, takes much longer to discharge than bit line BLx0. WLx0 must remain active (and PCx must remain inactive) until BLx1, the heaviest loaded bit line, is discharged. This time is shown as WLx0 Min in FIG. 1B.
One solution to the problem of wide loading variations on bit lines is found in IBM Technical Disclosure Bulletin, vol. 22, no. 8B, January 1980, by Williams and Wu, hereinafter Williams. In Williams, each bit line is guaranteed to never be loaded by switches controlled by more than half of the word lines. In Williams, if a bit line would be loaded by switches controlled by more than half the bit lines, the bit line personalization is changed to be controlled by all the switches that would not have controlled it, with an inversion added to the output of the bit line. For example, if a bit line were to be loaded by switches controlled by all of the word lines, the personalization of that bit line would be changed so that that bit line is loaded by no switches, and the bit line logically inverted prior to being driven as an output of the ROM. This technique requires an inverter to be available for each bit line, the inverter being used on any bit line requiring inversion as described above.
Therefore, there is a need for a method and apparatus that reduce the loading variation on bit lines in a ROM without requiring additional circuitry.